The present invention relates to a data processing apparatus for a virtual memory system which is capable of examining at a high speed whether the addresses of operands of instructions to be executed are susceptible to address translation.
In a computer system in which a virtual memory system is employed, data stored in a main memory device of the computer system is designated by logical addresses which are provided separately from the addresses (real addresses) which serve to indicate physical locations of the data. In this connection, the correspondences between the logical addresses and the real addresses are determined with the aid of an address translation table stored in the main memory. The address translation table in turn is supervised by an operating system.
When a given instruction is to be executed in the computer system outlined above, it is examined prior to the execution of the instruction to determine whether or not the logical address of the given instruction or relevant operand is susceptible of address translation, i.e., whether the logical address in concern is validly resident in the address translation table, whereby the instruction is allowed to be executed when the result of the examination has proven affirmative. This check or examination is referred to as a pretest.
Referring to FIG. 1 which shows in a functional block diagram a typical address translation scheme, reference numeral 1 denotes a logical address register in which a logical address is loaded, numeral 2 denotes a real address register in which a real address resulting from the address translation is loaded, numeral 3 denotes an address translation table stored in a main memory device, and reference numeral 4 denotes an address translation buffer or TLB in which a portion or fragment of the address translation table is copied. As is known, the address translation is usually carried out on the basis of a space paged as a unit size, which space is commonly referred to as a page. Upon address translation, the significant or upper-order bits representing the page address of the logical address register 1 are translated to the page address of the real address register 2 through the address translation buffer 4 directly or with the aid of the address translation table 3, if demanded. On the other hand, the lower-order bits or less significant bits indicating the page displacement of the logical address register 1 are directly used as the page displacement of the real address register 2. The main memory device is accessed with the aid of the address loaded in the real address register 2.
The pretest memtioned hereinbefore is effected in the address translation scheme such as illustrated in FIG. 1.
Now, assuming that operands of variable length are stored in a main memory device and that an instruction is issued for processing operands each having the maximum length which does not exceed the size of a single page, a procedure for executing the pretest of these operands will be elucidated below by referring to FIG. 2.
In FIG. 2, there is illustrated the paged state in which a first operand and a second operand are stored in the main memory device. As can be seen from the figure, the first operand labelled "1 op" is stored extending consecutively from page 1 to next page 2, while the second operand labelled "2 op" is stored over page 3 and page 4 in continuity. The consecutive storage or entry of an operand over two adjacent pages in this manner is referred to as the inter-page consecution of an operand. In this illustrated case, a check of the first operand "1 op" must be made for the two pages 1 and 2, while the check of the second operand "2 op" has to be made over the two pages 3 and 4. Accordingly, the pretest as to whether the address translation is possible (i.e. address translatability) or not must be carried out as many as four times.